Non-Volatile Processor Design for Self-Powered Embedded Systems

In recent years, embedded systems have widely spread into major industries, e.g., consumer electronics, mobile communications, and automotive. A large share of embedded systems rely on batteries and/or energy harvesting as their supply of energy which imposes a crucial design bottleneck and adversely affects system's performance, processing progress, and longevity. Non-Volatile Processors (NVP) are an emerging class of processors which address these issues using Non-Volatile Memory (NVM) technologies and distributed hibernation mechanisms. Despite their non-volatility support, NVMs come with a series of technology-inherent shortcomings, e.g., low endurance (high degradation), high variability, and write energy consumption which must be addressed throughout the hierarchy of NVP design process. To that end, this dissertation focuses on the Resistive RAM (ReRAM) technology as a promising NVM solution for NVP design and proposes a collection of models, designs, structures, and techniques to address ReRAM shortcomings at different levels of NVP design hierarchy. At the device level, an approach for ReRAM variability fitting is presented which enables accurate simulation of ReRAM behavior throughout the design hierarchy levels from circuit-level simulations to system-level evaluations. At the circuit and gate levels, novel structures for ReRAM-based Non-Volatile Unit (NVU) and Non-Volatile Flip-Flop (NVFF) are presented which address the major ReRAM shortcomings and serve as the fundamental components for NVP design. At the architecture and system levels, this work focuses on architecture exploration and presents a novel technique for early-stage hibernation evaluation of NVPs in terms of energy efficiency and degradation. The contributions of this work are supported by a comparative review of the related work and extensive experimental evaluations.